Rectifiers are used in AC-DC, DC-DC voltage converters, as well as in Switching Mode Power Supplies (SMPS). Typically, they are coupled to a secondary winding of a transformer for providing rectified half-waves to a load to be supplied, as shown in FIGS. 1-3.
Often, properly controlled MOSFETs are used as rectifiers instead of diodes because their power loss is smaller than that of diodes. A MOSFET is often referred to as a synchronous rectifier (SR). A synchronous rectifier is turned on and off by a dedicated control circuit for reproducing a diode voltage-current characteristic. The control signal of a synchronous rectifier is generally derived from a PWM control signal that determines the functioning states of the converter.
The way the control signal is derived from the PWM control signal depends upon the topology in use and on the presence of voltage isolation in the topology. In a non-isolated switched mode power supply topology, the synchronous rectifier control circuit can obtain the information about the switching transitions (turn-off and turn-on) of the main switch from the main control circuit in a very simple way. In isolated topologies with a primary side control, the absence of a PWM control signal on the secondary side of the isolation barrier makes the generation of control signals for the synchronous rectifiers more difficult.
If a synchronous rectifier does not function as a diode, the well-known phenomena of cross conduction and shoot-through may occur. In all of these circumstances, one of the switches is forced to a conduction phase in the first quadrant of its voltage-current characteristic. Therefore, switching losses may become predominant, wasting most of the benefits introduced by the reduction of conduction losses by the rectifiers, or may even hinder a correct functioning of the circuit.
FIGS. 4 and 5 illustrate the turn-off waveforms of the control voltage (gate-source voltage) Vgs and the source current I of the synchronous rectifiers FW and FR after a step variation of the voltage Vs at the secondary winding of a transformer of a sample AC-DC or DC-DC converter, due to the turning on or off of a MOSFET in series to the primary winding of a transformer of a converter.
FIG. 6 illustrates time characteristics of the gate-source voltage Vgs, the source current I and the drain-source voltage of the synchronous rectifiers FW and FR when the rectifier FW is turned-off a short time before the voltage Vs in the secondary winding is switched high. The time interval from the trailing edge of the control voltage Vgs and the leading edge of the voltage Vs is herein referred as the “anticipation time”. It is desirable that this time not be a null so that the rectifier FW is already off when the rectifier FR is turned on, otherwise the secondary winding could be short-circuited.
Clearly, the control voltage Vgs of the rectifier FW (and evidently also of the rectifier FR) is generated as a function of the PWM signal that controls the switch in the primary side of the converter, or vice-versa.
The required timing of the control signals of a synchronous rectifier is shown in FIG. 7 for a converter formed according to a general switched-mode topology with one switch and only one diode. The conduction phases of the switch and the diode do not overlap each other. The shown dead time intervals prevent contemporary cross-conduction of the switch of the converter and the synchronous rectifier operating as a diode, but they need to be shortened as much as possible to minimize or reduce synchronous rectifier conduction times of the parasitic diode, and the consequent loss of efficiency. In fact, MOSFETs used as rectifying transistors may show poor performance because their parasitic diode (body-diode) is turned on at least during transitions between different states.
The functioning of the body-diode depends on the timing of the control signal, and in particular, on the turn-off instant of the synchronous rectifier with respect to the time interval in which the diode replaced by a MOSFET is supposed to be in a conduction state A to early turn-off of the synchronous rectifier is susceptible to cause an increase of conduction losses due to the body-diode, in which the whole current would flow. The switching losses caused by the reverse recovery current through the body-diode therefore depend on the current flowing through it at the instant in which the cathode-anode voltage VKA reverses.
In isolated topologies, if the control circuit that generates the PWM signal is at the secondary side, the task of controlling synchronous rectifiers may be easily addressed. In fact, the PWM signal available on the secondary side may be used to generate the driving signal for the synchronous rectifiers by adequately delaying edges of the PWM signal for compensating the propagation delays of the control signal transferred to the primary side of the converter through a dedicated coupling device.
The required timing for this kind of operation is shown in FIG. 8, in the more general case of two complementary signals on the secondary side. The control signal of a MOSFET in the primary side of the converter is generated with a slight delay ΔTp1, ΔTp2 from the PWM signal, while the edges of the control signals of the rectifiers FW and FR of the converter of FIG. 5 are delayed by larger delays ΔT1 and ΔT2, respectively. Even in this case, dead times between drive signals are necessary to prevent an eventual cross conduction between two synchronous rectifiers and between an synchronous rectifier and a switch of the converter.
However, secondary side control configurations show several drawbacks. One drawback is the need of an auxiliary power supply for the start-up of the converter for a crossing-isolation circuit being able to transfer the PWM signal of synchronous rectifying transistors to switches on the primary side of a converter. Another drawback is in transferring the information regarding the current on the primary switch to the PWM controller in current mode control loops. Therefore, the use of a PWM control signal on the primary side of a converter is mandatory to form switched mode power supplies (SMPS) with high performance in terms of high efficiency, small dimensions and low cost.
In isolated topologies, if the control circuit that generates the PWM signal is on the primary side of a converter, then the PWM signal cannot be available on the secondary side in a simple, effective and low cost manner. This information may be derived at the secondary side from the output of the isolation transformer of the converter.
In this case, however, the synchronizing signal at the output of an isolation transformer is the effect of primary main switch commutations. This signal, in fact, is equalized to the PWM signal in a continuous conduction mode (CCM), but it is negatively affected by the parasitic elements of the circuit that distort its waveform.
The delay in the propagation chain of the signal derived by the PWM signal makes it not suitable to control the synchronous rectifier on the secondary side. This is because the delay control makes the switch and the synchronous rectifier of the converter be in a conduction state at the same time.
Methods and relative control circuits capable of generating a control voltage for a synchronous rectifier with the desired anticipation time in order to turn-off the synchronous rectifier before a switch of the converter is turned on have been developed in different ways.
A first technique is described in U.S. Pat. No. 6,418,039. The pulses of a high frequency oscillator (HFO) (more than 100 times the main converter switching frequency) are counted during each switching period of a PWM signal, and the anticipation time is determined by decreasing/increasing the counting obtained during the previous switching period.
The main advantage of this technique is that the system is very fast to face eventual transient conditions, because the counting is updated at each switching period,
The main drawback is that the digital counting causes an output jitter, the width of which is twice the period of the HFO. Unfortunately, the minimum anticipation time is determined by the frequency of the HFO, thus the HFO frequency needs to be increased for obtaining low anticipation times. Therefore, this technique is likely to increase power dissipation and requires counters with a relatively large end-scale count.
An analog method to generate the anticipations of the turn-off transition in the driving timing has been disclosed in the U.S. Pat. No. 5,736,890, implemented in a circuit by SRMOS Inc. According to this method, two different analog ramps and one threshold variable with TON or TOFF are used for generating the anticipation time. Three passive components (capacitors) are needed to generate the ramps and the variable threshold. Two of these capacitors need to be accurate to have a precise anticipation time.
Stability in time and in temperature is not good because of the presence of passive components. To obtain very short anticipation time values, the capacitors need to be determined very accurately. In case of capacitor value variations due to unpredictable events (temperature changes, capacitor life, etc.) this anticipation time can be lost causing cross conduction problems.
Another control technique that uses a Phase Lock Loop (PLL) based system for establishing the desired time anticipations of the turn off transitions has been recently implemented by International Rectifier in the integrated circuit IR1175.
This method is quite complex in terms of design relations needed to obtain the desired control. It requires many external components and has a relatively high pin count to set the parameters that are necessary for correctly implementing the control technique. Moreover, a drawback of this method is a slow response time to switching frequency variations. Should a noise cause a variation of the switching frequency, the PLL would react too slowly to this variation.
As a consequence, the anticipation times would be inaccurately determined and this would reduce the overall efficiency of the converter. A faster response time may be achieved at the cost of worsening the accuracy with which the anticipation time is determined, which would negatively affect the efficiency of the converter.